A design technique is known in which a test circuit is incorporated at a design stage in advance to check whether or not a delay fault or a stuck-at fault has occurred in a product, after manufacture of a semiconductor integrated circuit. Such a design technique is called a Design for Testability (DFT).
A “scan design” is known as one scheme of the design for testability. According to the scan design, all or a part of flip-flops in a designed circuit is replaced by scan cells (also, to be referred to as scan flip-flops) and constitutes a scan chain (also, to be referred to as a scan path).
Referring to FIG. 1, a scan chain will be described. The scan chain is configured from using flip-flops FF1 to FF4 provided between combinational circuits C1 to C3 in the semiconductor integrated circuit. Specifically, an output terminal of each of the flip-flops FF1 to FF4 is connected with an input terminal of the next flip-flop through one of selectors (multiplexers) M1 to M4, and the respective flip-flops FF1 to FF4 function as scan cells 1 to 4. The scan cells 1 to 4 are connected in series and constitute a scan chain operating as a shift register. The scan chain captures a scan-in test pattern data to supply to a combinational circuit by a shift operation. In addition, the scan chain captures data D1 to D4 from the combinational circuits on the basis of a scan enable signal SE, and outputs the captured data by the shift operation.
A signal selecting operation of the selectors M1 to M4 is controlled based on the scan enable signal SE, which switches the operation between a capture operation (a data input operation) and the shift operation. For example, the scan cell 1 captures the data D1 from the combinational circuit C1 through the selector M1. The captured data D1 is shifted to the next-step scan cells 2, 3, and 4 in accordance with the scan-in data SI, and is retrieved outside as a scan-out data SO. The scan cells 2 to 4 operate in the same manner.
In the scan test, the test pattern data is supplied to the combinational circuit by the shift operation of the scan chain, and the output data of the combinational circuit is retrieved from the scan cell (flip-flop) through the capture operation. Next, the output data retrieved to the scan cell is outputted outside through the shift operation. By comparing the data retrieved in this manner (scanned-out data) with an expectation value, whether or not a logic circuit in a test target circuit is in a good state can be checked.
Referring to FIG. 2, details of operation of the scan test in a conventional technique will be described. FIG. 2 is a diagram showing an example of the scan chain. Here, the scan chain having eight scan cells 1 to 8 will be described as one example. At first, the test pattern data is set to (scanned in) the scan chain, and a response result is retrieved to (captured by) each of the scan cells 1 to 8.
The captured result is retrieved (scanned out) outside through the shift operation. In accordance with the shift operation in scanning-in or scanning-out the data, a data value retained in the scan cell varies (toggles). When the number of times of the toggling operation (toggling count) is large, power consumption amount increases. Accordingly, the toggling count can be reduced by setting the value of data scanned in the scan chain (scan-in data SI) to be adequate, and thus an increase of the power consumption amount can be suppressed.
As one example of the method of reducing the toggling count, a same-value-Fill method is known. The same-value-Fill method is a method of scanning-in a scan-in data of a pattern in which a don't-care bit is set to the same value as that of a care bit. Here, the care bit indicates a bit position corresponding to a scan cell necessary for fault detection in the pattern data. The same-value-Fill is sometimes called minimum transition fill, repeat fill, or adjacent fill.
For example, in a scan chain shown in FIG. 2, when fourth and eighth scan cells 4 and 8 from a scan-in side are used for the fault detection, a position of each of the cells on the pattern is set as the care bit. In this case, the pattern data is scanned-in in which the first and fifth bits are the care bits and the other bits are the don't-care bits. For example, when the data value of the first bit is “1” and the data value of the fifth bit is “0”, the don't-care bits of the second to fourth bits are set to “1” which is same as that of the first bit, and the don't-care bits of the sixth to eighth bits are set to “0” which is same as that of the fifth bit. That is, the pattern data “11110000” is scanned-in.
When the pattern data is set to the scan cells 1 to 8 by using the same-value-Fill method, the same bit data is consecutively supplied to the scan cell through the shift operation. In this manner, the toggling count in the scan cell is reduced and the power consumption amount in the scan-in is suppressed. A method of reducing the toggling count using the same-value-Fill method is described, for example, in “SYSTEM ON CHIP TEST ARCHITECTURES” (MORGAN KAUFFMAN, NOV, 2007) by Lasing-Terng Wang, Charles E. Stroud, and Nur A. Touba.
Since a pattern of the scan-in data SI can be arbitrarily set by a user (a designer), the toggling count can be reduced by using the same-value-Fill method as described above. However, since the capture data is a random data that cannot be arbitrarily set, it is difficult to control the toggling count of the scan cell based on the scan-out data.
As described above, in the conventional technique, the power consumption amount in the scan-in can be reduced; however, it is difficult to reduce the power consumption amount in the scan-out for retrieving the captured data. To reduce the power consumption amount in the scan test, it is desired to reduce the power consumption amount in the scan-out.